详细介绍：

中文名称：synopsys.Design.Compiler.2000.v5.nt
英文名称：synopsys.Design.Compiler.2000.v5.nt
资源类型：ISO
版本：2000 for nt
发行时间：2000年
制作发行：synopsys
地区：美国
语言：英语
简介：
[通过安全测试]
杀毒软件：symantec
病毒库：2006-3-15
通过安装测试]WindowsXP SP2
软件版权归原作者及原软件公司所有，如果你喜欢，请购买正版软件
这是本软件windows平台最后一个版本, 最新版本都为unix版.


破解说明:
Synopsys Design Compiler 安装指南：

1.运行安装文件，按照提示进行安装过程。
2.必须安装scl_1_1_NT，才能使License.dat起作用。
3.把license file的前面两行改为如下：

SERVER this_host ANY 27000
VENDOR snpslmd D:\scl\msvc50\bin\snpslmd.exe
^^^这是scl（synopsys common license 的安装目录）
然后设置环境变量($HOME)。
将License.dat拷贝到 C:\flexlm 目录下
然后启动scl（开始->程序->synopsys products->Synopsys Common License
->flexlm.cpl
设置flexlm.cpl 窗口中的数据.
设置好各项变量，然后找到control-》start启动license sever就可以了。


Design Compiler
The Industry-Leading Synthesis Solution Is Now Even Better

Overview
Since 1988, Synopsys has focused on delivering state-of-the-art technologies such as gate-level synthesis, RTL synthesis, pre-verified DesignWare IP, integrated power & test optimization, advanced datapath optimizations, and physical synthesis, to provide you with the best tools that address your design needs－－innovation is synonymous with Design Compiler.

The latest innovation is topographical technology in Design Compiler Ultra that enables designers to accurately predict post-layout timing and area during RTL synthesis without the need for wireload model-based timing approximations. Created for RTL designers, Design Compiler Ultra with topographical technology requires no physical design expertise or changes to the synthesis use model. By accurately predicting post-layout timing and area, this solution eliminates costly iterations between synthesis and layout, providing faster time to results.

All of these advancements have resulted in a platform that delivers the fastest and smallest designs with lowest power and highest testability, now with the highest correlation to your back-end.

DC FLow


Key Benefits

* No need for wireload models (WLMs)
* Accurate prediction of post-layout timing and area
* Easy to adopt

Design Challenges
Increasing design complexity, shrinking geometries, higher clock speeds, and power reduction/test compression requirements have become mainstream, making timing and area, correlation between synthesis and layout more challenging than ever. Larger synthesis block sizes coupled with shrinking geometries are driving net delays to be the dominant factor in path delays. Million-gate synthesis block sizes make it much harder to estimate the net capacitances based on statistical information. This results in timing and area correlation issues, where the results after RTL synthesis do not correlate to post-physical implementation results. The challenge is amplified even further since place & route solutions cannot compensate for a bad start point handed to them from synthesis.

Solution
Topographical technology, the latest innovation in synthesis, delivers accurate correlation to post-layout timing and area, without wireload models. It is designed for RTL designers and requires no physical design expertise or changes to the synthesis use model. The accurate prediction of layout timing and area in Design Compiler Ultra is achieved through the innovative 搕opographical technology�. It enables RTL designers to fix real design issues while still in synthesis and generate a better start point for physical design, eliminating costly iterations. Topographical technology shares technology with Galaxy physical design ensuring a smooth, convergent path from RTL to GDSII.

As part of the Galaxy Design Platform, the optimal design creation solution in the industry, you benefit from the following:

* Best-in-class optimization with DC Ultra
* No need for wireload models with topographical technology
* Production-proven Test handoff with DFT Compiler and TetraMAX
* A complete power management solution with Power Compiler
* Industry-standard timing sign-off with PrimeTime
* The industry抯 largest IP repository with DesignWare

Related Products

* DFT Compiler
* DesignWare IP
* Formality
* IC Compiler
* Leda
* Physical Compiler
* Power Compiler
* PrimeTime
* System Verilog
* VCS
* Vera




这个帖子已被 yeziii 于 今天, 17:25 PM 编辑